Intel pulled back the curtain on Diamond Rapids, the next-generation Xeon 7 server processor, during its Hot Chips 2026 presentation. The flagship configuration tops out at 256 P-cores and 1.28 GB of last-level cache, with commercial availability in the data center set for 2027.
The architecture is built around a modular unit Intel calls a Compute Building Block, or CBB. Each CBB holds four core chiplets, and each chiplet carries 16 P-cores. A full Diamond Rapids system-on-chip stacks four CBBs, producing the 256-core total. Each core chiplet also gets private L2 cache, with L3 shared across the chiplet and located on the base tile beneath it.
Intel uses two distinct manufacturing nodes to build the chip. The 16 core chiplets are fabricated on Intel 18A-P, the enhanced variant of the company's 18A process. The four base tiles that hold the last-level cache use Intel 3-T. The two fabric hub tiles that handle cross-chip communication are built on Intel 3. That three-node split reflects Intel's strategy of matching the process node to the function of each die rather than forcing everything onto a single process.
Within each CBB, Intel bonds the core chiplets to the base tiles using Foveros Direct 3D, the same copper-to-copper bonding method used in the Xeon 6+ Clearwater Forest processors. Across the chip, the CBBs connect to two centralized fabric hub tiles via UCIe-S, a copper interconnect built on the Universal Chiplet Interconnect Express standard. Intel explicitly dropped its own Embedded Multi-die Interconnect Bridge, or EMIB, which had appeared broadly in previous product generations.
The UCIe-S connection handles what Intel calls 2D communication—the lateral signaling between CBBs and the fabric hubs. Even though each CBB uses 3D stacking internally, the inter-CBB path runs horizontally through the fabric hubs. Each of the four CBBs connects to both fabric hubs, so no core cluster is dependent on a single communication path.
The overall layout represents a structural reversal from Granite Rapids, Intel's current high-end server processor. In Granite Rapids, memory and I/O subsystems are distributed; Diamond Rapids centralizes them. Intel did not fully detail the Panther Cove core microarchitecture—the actual CPU core design inside each chiplet—during the Hot Chips presentation, reserving that disclosure for before the 2027 launch.
The 256-core ceiling is notable. AMD's top EPYC Venice processor, the direct competitor, also reaches 256 cores at its flagship configuration. Intel arriving at parity on raw core count marks a shift from the prior generation gap. Earlier leaks had suggested Diamond Rapids would reach 512 cores at the high end; those configurations are no longer in the disclosed roadmap.
For the data center market, the economics of Diamond Rapids hinge on what the 18A-P process delivers in performance-per-watt relative to AMD's EPYC Venice and against Arm-based server chips from Ampere and AWS Graviton. Intel has not released power figures or benchmark results. The 1.28 GB of last-level cache is substantial—EPYC Genoa, AMD's current generation, carries up to 768 MB of L3—and cache size directly affects latency-sensitive workloads like in-memory databases and AI inference on CPU.
The AVX 10.2 instruction set support, confirmed for Diamond Rapids, extends Intel's vector processing capabilities. AVX instructions accelerate floating-point math used in machine learning inference, signal processing, and scientific computing. Version 10.2 adds capabilities beyond the AVX-512 standard that Intel's current server chips support, though Intel has not yet published a full specification breakdown for what 10.2 adds over 10.1.
Nvidia's data center GPU revenue has dominated the AI infrastructure conversation for two years, but CPU vendors are competing for inference workloads where latency requirements and batch sizes do not justify GPU allocation. A 256-core CPU with 1.28 GB of on-chip cache is a direct bid for that segment. Nvidia's H100 and H200 GPUs remain the default choice for training and large-batch inference; CPUs compete on cost-per-query for smaller, latency-sensitive inference jobs.
The architecture's use of UCIe-S instead of EMIB signals where Intel is taking its multi-die strategy—UCIe is an open industry standard, and building to it rather than a proprietary bridge opens Intel's packaging ecosystem to third-party chiplets over time.
With Panther Cove core details still undisclosed and no power or performance numbers on the table, Diamond Rapids remains an architecture on pa. Intel's 2027 commercial target gives it roughly 18 months to close the remaining technical disclosures and demonstrate that 18A-P yields at the scale a 16-chiplet server chip demands.
