Kioxia has unveiled its Multi-Stacked Array with CMOS Bonded Array (MSA-CBA) design for ultra-high-density 3D NAND flash memory, branded as BiCS Flash. The architecture uses copper direct bonding to stack multiple 218-layer cell array wafers onto a CMOS wafer—a critical engineering step toward 1,000-plus-layer devices.
The separation of cell array manufacturing from peripheral CMOS circuitry allows independent optimization of each component, which can improve yields and performance. Copper direct bonding provides high-density, low-resistance interconnections between stacked wafers, maintaining signal integrity and power efficiency as layer counts scale.
Prototype devices have demonstrated Quad-Level Cell (QLC) operation, storing four bits per cell. For hyperscalers, this density directly improves cloud storage margins. Kioxia's prototypes also showed high-temperature data retention—a reliability requirement for enterprise data centers.
The competitive landscape is brutal. Samsung and SK Hynix are advancing their own 3D NAND stacks. Western Digital, Kioxia's joint venture partner, gains access to these improvements. But the economics matter more than the architecture: achieving 1,000-plus layers drives down cost-per-gigabyte, directly altering capex calculations for anyone running scale-intensive data center operations.
Manufacturing advanced 3D NAND requires sustained capex and R&D firepower. Kioxia's move signals the ongoing race to deliver higher capacity at lower cost—a necessity as AI workloads push data storage demand beyond prior growth rates. Whoever executes this manufacturing complexity at scale wins durable share in a market where cost-per-bit is the only metric that matters.
