Ricursive Intelligence founders Anna Goldie and Azalia Mirhoseini presented their AI-driven chip design strategy at TechCrunch Disrupt on Wednesday, Oct. 14. The company develops artificial intelligence capable of designing chips, learning from iterations, and improving subsequent designs to automate and accelerate the process.
Goldie projected surging demand for compute power. "In the next five years we are going to have at least 10,000x more demand for compute, and that's somewhat potentially conservative," she said. Instead of building 10,000 times more data centers, she argued for more efficient chips that optimize bandwidth, wafer utilization, and fab capacity.
The core premise: AI handles execution, freeing humans to focus on creative ideas and new applications. "Humans bring their great ideas and creative thoughts, and execution is handled by AI," Goldie explained. "This is happening in chip design, software development, and other places." Ricursive applies this model directly to chip architecture.
Traditional chip design partitions circuits into dozens of smaller blocks. Ricursive optimizes entire chips holistically, allowing the AI to discover unconventional layouts that human engineers might never consider. An earlier system developed by the founders, AlphaChip, created a circular, donut-shaped component arrangement that surprised engineers but proved superior to conventional designs. The AI has also generated wave-like patterns in layouts.
The speed advantage is material. Chip design typically takes six months to two years—a cost that must be amortized across high production volumes. "If you can design a chip in like a week, then you can design custom chips for all sorts of different types of applications in space and AR, VR, and biological computing, and it makes sense financially to do that," Goldie said. Faster iteration reduces upfront capital risk and unlocks markets previously uneconomical for custom silicon.
The model reshapes the economic logic of specialized processors. Applications in augmented reality, virtual reality, space technology, and biocomputing—which demand highly optimized, energy-efficient designs—become commercially viable. Shorter design cycles mean engineering resources and fab capacity can move faster between projects, increasing utilization.
The efficiency angle addresses a concrete problem: data center power consumption. More efficient chips reduce the infrastructure and electricity costs required to handle a 10,000x surge in compute demand. For cloud providers and AI model trainers facing GPU bottlenecks and rising power bills, application-specific silicon designed for their workload mix could shift the unit economics of training runs and inference serving.
