Intel laid out the physical design of its Diamond Rapids Xeon 7 processor at Hot Chips 2026, giving the data center industry its first detailed look at a chip that won't ship until 2027 but whose architecture signals a direct competitive challenge to AMD's EPYC roadmap.

The full package carries 22 chiplets in total. Sixteen are CPU compute tiles, each holding 16 Panther Cove P-cores, for a maximum core count of 256. The remaining six tiles split into two categories: four base tiles that hold cache and two central Fabric Hub tiles that handle memory and I/O. The six non-CPU tiles are not built on Intel's newest process.

The 16 CPU chiplets use Intel's 18A-P process node—the production variant of 18A, the node Intel has staked its foundry revival on. Getting 16 chiplets of 18A-P silicon onto a single package is a manufacturing challenge as much as a design statement. Intel connects those CPU tiles to the four base tiles using Foveros Direct 3D packaging, a die-stacking approach that bonds chips face-to-face at fine pitch rather than relying on traditional side-by-side interposers.

Each of the four base tiles carries 320MB of L3 cache. Across the package, that totals 1.28GB of last-level cache—substantially more than any current-generation Xeon and a calculated bet on workloads where data reuse directly determines throughput: large in-memory databases, finite-element simulation and certain AI inference jobs that don't fit neatly on a GPU.

For interconnect between major package components, Intel chose UCIe-S, the server variant of Universal Chiplet Interconnect Express, rather than the Embedded Multi-die Interconnect Bridge used in earlier Xeon designs. UCIe-S is a standardized die-to-die interface that other chiplet vendors can implement, enabling composable server designs where customers mix compute, memory and accelerator tiles from different suppliers.

Memory bandwidth gets a substantial increase. Diamond Rapids supports 16 memory channels—double what most current two-socket server platforms offer—running DDR5-8000 or MRDIMMs at up to 12,800 megatransfers per second. Intel cites aggregate memory bandwidth of 1.6 terabytes per second from that configuration. For HPC workloads that are memory-bandwidth-bound rather than compute-bound, that number is the headline spec, not core count.

Diamond Rapids provides 128 PCIe Gen 6 lanes—which doubles per-lane bandwidth versus Gen 5—alongside CXL 3.0 and UPI 3 for inter-socket communication. An additional eight PCIe Gen 4 lanes round out the platform. That bandwidth envelope allows the processor to feed multiple GPUs or CXL memory expansion devices simultaneously without the interconnect becoming the bottleneck.

On the instruction set side, Diamond Rapids adds AVX 10.2, an updated Advanced Matrix Extensions—AMX, an on-die accelerator for matrix math used in neural network inference—and APX extensions, which add 16 general-purpose registers to the x86 architecture to reduce the memory traffic from register spilling during computation. Intel has not yet disclosed clock speeds, thermal design power or detailed Panther Cove microarchitecture specifications.

AMD's EPYC Venice, the next-generation server chip AMD is building toward, also targets 256 cores at its top configuration. Both companies are converging on the same core count from different chiplet strategies. AMD uses TSMC; Intel is betting that 18A-P on its own fabs, combined with Foveros Direct stacking, produces a better cache-to-core ratio and lower latency than a TSMC-assembled chiplet design.

Diamond Rapids succeeds Granite Rapids, Intel's current high-core-count Xeon. Granite Rapids was designed to recapture ground Intel lost to AMD's EPYC Genoa and Bergama generations, which arrived with higher core counts and competitive memory bandwidth before Intel could respond. Diamond Rapids is Intel's answer two product cycles later. Its 2027 launch window means hyperscalers writing infrastructure roadmaps today are already choosing between committing to the current generation or waiting.

For Intel's foundry business, the 18A-P production on Diamond Rapids serves a second purpose beyond the chip itself. Filling fab capacity with 16-tile lots of a high-volume server processor generates the yield data and process maturity Intel needs to show external customers that 18A-P is ready for commercial orders. Intel shares rose 2.2 percent on Aug. 26, tracking a broader tech rally—a reminder that hyperscaler capital expenditure is rising and the infrastructure buildout driving server CPU demand continues.