Leading-edge device makers plan to introduce complementary field effect transistors (CFETs) in the coming years, a move expected to significantly enhance chip density. This new architecture stacks p-type and n-type transistors one atop another, nearly doubling the transistor density compared to current lateral nanosheets.
The industry anticipates CFETs will deliver a 40 percent improvement in packing density, a 50 percent leap in performance, and potentially a 70 percent gain in efficiency. This vertical stacking is particularly compelling for SRAM designs, where it can enable a transition from a 6T to a more compact 4F2 construction.
CFET technology's primary advantage stems from eliminating physical spacing constraints between NMOS and PMOS transistors. This allows for a silicon footprint reduction of up to 50 percent for a 6T-SRAM cell, according to early research.
Process qualification for CFETs remains years away, with industry experts not expecting production until approximately 2031. The development requires optimizing materials and process flows for CFET gate-stack fabrication, a complex engineering challenge.
Significant hurdles include establishing the necessary vertical connections for signal and power lines to, from, and between transistors, as well as the wafer backside. Even minor misalignments can lead to substantial manufacturing issues.
"When you talk about nanosheets, they are just so small. There's almost no room for variation," said Joseph Ervin, managing director of Semiverse Solutions at Lam Research. "A two-nanometer misalignment can cause a big manufacturing problem."
Major chipmakers TSMC, Intel, Samsung, and IBM are pursuing slightly varied approaches to CFET construction. IBM uses a sequential flow, fully fabricating the first set of transistors before the second set, with a slight offset.
Most other companies are exploring monolithic process flows, where the entire stack is built concurrently. Intel is investigating both monolithic methods and a hybrid-substrate approach that utilizes the most suitable silicon substrate for each transistor, aiming to boost the pFET, which historically performs less efficiently than the nFET.
TSMC has developed a backside gate contact and two types of vertical contact plugs to link different functional layers within SRAM bit cells. Samsung is working on a novel dielectric stack designed to separate the two gate regions.
Multi-physics simulation plays an increasing role in pathfinding and yield optimization for these new structures. "You have to balance every innovation with warpage and reliability," said Lalitha Immaneni, vice president at Intel assembly test technology development, noting the EDA ecosystem's focus on multi-physics modeling tools.
Historically, logic density scaled by 50 percent annually from 1998 to 2010, effectively halving SRAM area each year. Since 2010, scaling has approached a more linear pace, making the potential for a 50 percent overnight SRAM scaling with CFETs a significant future inflection point in chip architecture economics.
